docs(perception): record exact parity and fixed-envelope IPC comparison

docs/adr/0049-stream-first-perception-profiles.md

@@ -1,6 +1,6 @@
 # ADR 0049 — Stream-first full perception profiles
 
-Date: 2026-09-01; updated 2026-09-02 13:55 MSK. Status: stage-1 engineering
+Date: 2026-09-01; updated 2026-09-02 14:22 MSK. Status: stage-1 engineering
 baseline complete; stage-2 binary full-graph prototype, not a product runtime cutover.
 Execution order remains the four stages in
 [the ExecPlan](../OBSERVATORY_REALTIME_PROFILES_EXECPLAN.md).
@@ -243,6 +243,46 @@ Next: explain numerical reproducibility, measure/tune remaining pipeline tails,
 then complete controller/network/standalone boundaries within stage 2.
 No quality, physical-live, vehicle-control or real-time qualification is granted.
 
+Stage-2 numeric/IPC increment, 2026-09-02 14:22 MSK (`380b6ea`, `f39f1ff`):
+the two preceding raw range differences are resolved, not tolerated. A bounded
+CPU-only probe on Worker NumPy 1.26.4 reproduces both exact deviations using
+identical quaternion values at addresses 8 mod 16. The wire quaternion starts at
+byte 24 of a combined pose buffer; its norm changes by one ULP on that layout.
+Offsets 0/16/32/48 restore reference norm/rotation/depth, while 8/24/40/56 reproduce
+the deviations. The adapter now owns an immutable 32-byte quaternion copy and
+checks 16-byte alignment. Input bytes, projection algorithm and tolerances are
+unchanged. Other CPU/NumPy combinations still require numerical qualification.
+
+Synchronous local IPC now borrows contiguous image buffers. Decoder and parent
+no longer call BGR `tobytes()` for these handoffs; the sender writes framing and
+the borrowed body separately instead of concatenating a full message copy.
+Partial writes loop with explicit progress validation; noncontiguous buffers
+fail before output. The owner retains the image until send completes. This removes
+four application-level BGR copies across decoder→parent→DDRNet, not kernel copies,
+network bytes, or all intermediate allocations. Framing and lease/deadline checks
+are unchanged; a hung-decoder probe still fails and releases all owned resources.
+
+Preregistered sequential A–B–B–A at authorized temporary stock clock locks:
+all samples observed SM2610/memory10251 MHz, unchanged 8 CPU/8 GiB/power limit.
+Every run completes 128/128 without drops. Control p95/p99 84.702/92.961 and
+83.930/91.759 ms; candidate 85.113/91.219 and 82.425/90.530 ms. Both candidates
+match reference BGR, masks, objects, geometry/ranges, tracks, threats, materials,
+lineage/binding and raw costmap exactly on 128/128. Baselines still reproduce the
+two old float deviations. Median decoder RPC-minus-decode falls 1.642–1.825 to
+1.100–1.118 ms; DDRNet RPC-minus-component 2.109–2.217 to 1.558–1.613 ms.
+This is a modest IPC improvement; full p95 does not show an unambiguous win.
+The previous auto-clock 191.806-ms p99 cannot be compared as a copy-only baseline.
+
+Local 125-ms timing passes at this fixed operating envelope, but only 76/128
+scenes are fresh because the same 52 input sensor gaps remain. No overall or
+auto-clock/network/physical-live qualification is granted. Auto clocks and four
+Mission Core services are restored; Ollama/Frigate remain disabled. 279 focused
+tests pass. Manifest: 305 artifacts, SHA-256
+`9c72a93833a1dda51c4787dca13fb9791a1bf2e31c763b7740e1b21406703707`,
+`.runtime/perception-stage2-ipc-worker-20260902T1410MSK/manifest.json`.
+Next implementation boundary is the controller/envelope/network integration and
+standalone package. Host clock management is not granted implicitly to that controller.
+
 Open → validate bounded metadata/claim → warm models → Ready → start the replay
 clock → observations and incremental scenes → stop/drain bounded state → close
 and asynchronously seal the immutable receipt. A live source already producing